? semiconductor components industries, llc, 2006 october, 2006 ? rev. 9 1 publication order number: mc74hct04a/d mc74hct04a hex inverter with lsttl ? compatible inputs high ? performance silicon ? gate cmos the mc74hct04a may be used as a level converter for interfacing ttl or nmos outputs to high ? speed cmos inputs. the hct04a is identical in pinout to the ls04. features ? output drive capability: 10 lsttl loads ? ttl/nmos ? compatible input levels ? outputs directly interface to cmos, nmos and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1 a ? in compliance with the jedec standard no. 7a requirements ? chip complexity: 48 fets or 12 equivalent gates ? pb ? free packages are available http://onsemi.com marking diagrams a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb ? free package tssop ? 14 dt suffix case 948g 14 1 soeiaj ? 14 f suffix case 965 soic ? 14 d suffix case 751a 14 1 1 14 74hct04a alywg hct04ag awlyww 14 1 1 14 hct 04a alyw 1 14 1 4 1 pdip ? 14 n suffix case 646 mc74hct04an awlyywwg 1 14 see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information (note: microdot may be in either location)
mc74hct04a http://onsemi.com 2 logic diagram y1 a1 a2 a3 a4 a5 a6 y2 y3 y4 y5 y6 1 3 5 9 11 13 2 4 6 8 10 12 y = a pin 14 = v cc pin 7 = gnd pinout: 14 ? lead packages (top view) 13 14 12 11 10 9 8 2 1 34567 v cc a6 y6 a5 y5 a4 y4 a1 y1 a2 y2 a3 y3 gnd l h function table inputs outputs a h l y ordering information device package shipping ? mc74hct04an pdip ? 14 25 units / rail mc74hct04ang pdip ? 14 (pb ? free) mc74hct04ad soic ? 14 55 units / rail mc74hct04adg soic ? 14 (pb ? free) mc74hct04adr2 soic ? 14 2500 / tape & reel mc74hct04adr2g soic ? 14 (pb ? free) mc74hct04adtr2 tssop ? 14* MC74HCT04ADTR2G tssop ? 14* mc74hct04afel soeiaj ? 14 2000 / tape & reel mc74hct04afelg soeiaj ? 14 (pb ? free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc74hct04a http://onsemi.com 3 ??????????????????????? ??????????????????????? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? v cc ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 20 ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 25 ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 50 ??? ??? ???? ? ?? ? ???? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air plastic dip? soic package? tssop package? ????? ? ??? ? ????? 750 500 450 ??? ? ? ? ??? mw ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? c ???? ? ?? ? ???? t l ?????????????? ? ???????????? ? ?????????????? lead temperature, 1 mm from case for 10 seconds plastic dip, soic or tssop package ????? ? ??? ? ????? 260 ??? ? ? ? ??? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ?derating ? plastic dip: ? 10 mw/ c from 65 to 125 c soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d). recommended operating conditions ???? ???? ?????????????? ?????????????? ??? ??? ??? ??? ??? ??? ???? ???? v cc ?????????????? ?????????????? ??? ??? ??? ??? ??? ??? ???? ???? ?????????????? ?????????????? ??? ??? ??? ??? ??? ??? ???? ???? ?????????????? ?????????????? ??? ??? ??? ??? ??? ??? c ???? ???? ?????????????? ?????????????? ??? ??? ??? ??? ??? ??? dc characteristics (voltages referenced to gnd) v cc v guaranteed limit symbol parameter condition ? 55 to 25 c 85 c 125 c unit v ih minimum high ? level input voltage v out = 0.1v |i out | 20 a 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum low ? level input voltage v out = v cc ? 0.1v |i out | 20 a 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 v v oh minimum high ? level output voltage v in = v il |i out | 20 a 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 v v in = v il |i out | 4.0ma 4.5 3.98 3.84 3.70 v ol maximum low ? level output voltage v in = v ih |i out | 20 a 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih |i out | 4.0ma 4.5 0.26 0.33 0.40 i in maximum input leakage current v in = v cc or gnd 5.5 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 5.5 1 10 40 a i cc additional quiescent supply current v in = 2.4v, any one input v in = v cc or gnd, other inputs i out = 0 a 5.5 ? 55 c 25 to 125 c ma 2.9 2.4 1. information on typical parametric values can be found in chapter 2 of the on semic onductor high ? speed cmos data book (dl129/d). 2. total supply current = i cc + i cc . this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hct04a http://onsemi.com 4 ac characteristics (v cc = 5.0v 10%, c l = 50pf, input t r = t f = 6ns) guaranteed limit symbol parameter ? 55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a to output y (figures 1 and 2) 15 17 19 21 22 26 ns t tlh , t thl maximum output transition time, any output (figures 1 and 2) 15 19 22 ns c in maximum input capacitance 10 10 10 pf 3. for propagation delays with loads other than 50 pf, and information on typical parametric values, see chapter 2 of the on sem iconductor high ? speed cmos data book (dl129/d). c pd power dissipation capacitance (per inverter)* typical @ 25 c, v cc = 5.0 v pf 22 * used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d). figure 1. switching waveforms gnd 3.0v output y input a c l * *includes all probe and jig capacitance test point 90% 1.3v 10% t tlh device under test output figure 2. test circuit y a figure 3. expanded logic diagram (1/6 of the device shown) t thl 2.7v 1.3v 0.3v t plh t phl t f t r
mc74hct04a http://onsemi.com 5 package dimensions pdip ? 14 case 646 ? 06 issue p 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m ??? 10 ??? 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ? t ? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87
mc74hct04a http://onsemi.com 6 package dimensions soic ? 14 case 751a ? 03 issue h notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint* 7x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hct04a http://onsemi.com 7 package dimensions tssop ? 14 case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hct04a http://onsemi.com 8 package dimensions soeiaj ? 14 case 965 ? 01 issue a h e a 1 dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.004 0.008 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 1.42 ??? 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc74hct04a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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